FIG. 8 shows a bias circuit illustrated in FIG. 5 of Japanese Patent Laid-Open No. 2005-101733. The bias circuit includes three bipolar transistors Q1 to Q3 and three resistors R1 to R3, and a bias current is supplied from the emitter of the bipolar transistor Q2 constituting a collector ground circuit (emitter follower). Hereinafter, the bipolar transistors Q1 to Q3 will be referred to as transistors Q1 to Q3.
In the bias circuit, a reference voltage Vref is applied in common to the bases of the transistors Q1 and Q2 from a power supply terminal 7 through the resistor R3.
When the reference voltage Vref is 0 V, the base potentials of the transistors Q1 and Q2 are also 0 V, so that there is no potential difference between the bases and emitters of the transistors Q1 and Q2 and a current Idc is not generated that flows from a power supply terminal 4 to the collectors of the transistors Q1 and Q2. Thus the supply of a bias current is stopped.